This invention relates generally to semiconductor chip device assembly, and in particular to flip chip device assembly. More specifically, the invention relates to a flip chip device assembly process that integrates solder joining and underfill operations.
In semiconductor device assembly, a semiconductor chip (also referred to as an integrated circuit (IC) chip or xe2x80x9cdiexe2x80x9d) may be bonded directly to a packaging substrate, without the need for a separate leadframe or for separate I/O connectors (e.g., wire or tape). Such chips are formed with ball-shaped beads or bumps of solder affixed to their I/O bonding pads. During packaging, the chip is xe2x80x9cflippedxe2x80x9d onto its active circuit surface so that the solder balls form electrical connections directly between the chip and conductive pads on a packaging substrate. Semiconductor chips of this type are commonly called xe2x80x9cflip chips.xe2x80x9d
In a conventional method for packaging a semiconductor flip chip a semiconductor die and a packaging substrate are electrically connected and mechanically bonded in a solder joining operation. For example, an unbonded flip chip may have an array of solder balls or bumps arranged on its active circuit surface. The solder is generally composed of a eutectic material having a melting point of about 180xc2x0 C. or a higher melting lead material, having a melting point of about 300xc2x0 C., for example. Dies may have dimensions on the order of about 5-30 mmxc3x975-30 mm.
Prior to bonding the die to a substrate, solder flux is applied to either the active surface of the die or the packaging substrate surface. The flux serves primarily to aid the flow of the solder, such that the solder balls make good contact with pads or presolder on the packaging substrate. It may be applied in any of a variety of methods, including brushing or spraying, or dipping the die into a thin film, thereby coating the solder balls with flux. The flux generally has an acidic component, which removes oxide barriers from the solder surfaces, and an adhesive quality, which helps to prevent the die from moving on the packaging substrate surface during the assembly process.
After the flux is applied, the die is aligned with and placed onto a placement site on the packaging substrate such that the die""s solder balls are aligned with electrical pads on the substrate. The substrate is typically composed of a laminate or organic material, such as fiber glass, PTFE (such as Teflon(trademark), available from Gore, Eau Claire, Wis.) BT resin, epoxy laminates or ceramic-plastic composites. Heat (to a temperature of about 200-300xc2x0 C., for example, depending on the type of solder material) is applied to one or more of the die and the packaging substrate, causing the solder balls to reflow and form electrical connections between the die and the packaging substrate. The package is then cooled to harden the connection. Then, the remaining flux residue is substantially removed in a cleaning step, for instance by washing with an appropriate solvent.
At this point in a conventional assembly procedure, an underfill is applied in order to enhance the mechanical bonding of the die and substrate. An underfill material, typically a thermo-set epoxy, such as is available from Hysol Corporation of Industry, Calif.(product numbers 4511 and 4527), Ablestik Laboratories of Rancho Domingo, Calif., and Johnson Matthey Electronics of San Diego, Calif., is dispensed into the remaining space (or xe2x80x9cgapxe2x80x9d) between the die and the substrate. In a typical procedure, a bead of thermo-set epoxy, is applied along one edge of the die where it is drawn under the die by capillary action until it completely fills the gap between the die and the packaging substrate. Slight heating of the packaging substrate after dispensing of the underfill epoxy may assist the flow. In some cases, the underfill epoxy flow is further assisted by vacuum, or, alternatively, by injection of the epoxy into the gap.
Thereafter, the underfill is cured by heating the substrate and die to an appropriate curing temperature for the underfill material, generally in the range of about 120 to 180xc2x0 C., and then cooled. In this manner the process produces an electrically and mechanically bonded semiconductor chip assembly, with the underfill material allowing a redistribution of the stress at the connection between the die and the substrate from the solder joints only to the entire sub-die area.
A problem with such flip chip package constructions is that during the cool down from the solder joining temperature, the whole package is highly stressed prior to application and curing of the underfill material due to the different coefficients of thermal expansion (CTEs) of the substrate and die materials. Shrinkage of the substrate, typically having a CTE of about 17 ppm, is much more than that of the die, which typically has a CTE of about 2-3 ppm, e.g., 2.6 ppm. The high stress experienced by these bonded materials during cooling may cause them to warp delaminate or crack. Such stress in the semiconductor package may ultimately result in its electronic and/or mechanical failure, including cracking of the die, substrate or their solder electrical connections. This problem is particularly acute for larger die sizes, for example dies having dimensions at or in excess of 20 mm on a side, which are presently being fabricated and packaged (e.g., Altera Corporation""s 2A70 die which is 23 mmxc3x9728 mm). For such large die sizes, the stress induced by the cooling following solder joining before underfill is even applied and cured may cause cracking in the die or substrate.
Accordingly, what is needed are flip chip device assembly methods that reduce physical stresses that may lead to die or substrate crack formation, particularly for large die sizes.
To achieve the foregoing, the present invention provides flip chip device assembly methods that integrate the solder joining and underfill operations of the assembly process. Solder joining of the die and substrate and curing of the underfill material between the die and substrate is accomplished in the same heating and cooling operation. As a result, the coefficient of thermal expansion (CTE) mismatch stresses incurred prior to application and curing of underfill by a device packaged according to the conventional technique having a separate heating and cooling operation following solder joining, are avoided. These stresses are of particular concern in smaller device size technologies (e.g., 0.13 microns and smaller) using low k dielectrics and large die sizes due the difference in CTE between the die and substrate.
In order to have the underfill material available in place for curing during the same heating and cooling operation that is used for solder joining, a number of different approaches for disposing the underfill material may be used. These include introduction of a liquid phase (or suspension) underfill material between an aligned die and substrate by capillary action, application of a liquid phase (or suspension) underfill material to the die and/or substrate around the solder ball positions of the solder ball array to be used to solder join the die and substrate, such as by using a stencil, prior to alignment of the die and substrate for solder joining, and application to the die or substrate prior to alignment of the die and substrate for solder joining of a solid phase underfill material predrilled to accommodate the solder ball array to be used to solder join the die and substrate. In the case of the introduction of underfill material by capillary action, preheating to a temperature below that sufficient to induce curing of the underfill material may be conducted to facilitate the capillary action.
In one aspect, the invention relates to a method of assembling a semiconductor die with a packaging substrate. The method involves providing a flip chip die and a packaging substrate, disposing an uncured underfill material between the die and the substrate, and then curing the underfill material during solder joining of the die and the substrate.
These and other features and advantages of the present invention are described below where reference to the drawings is made.